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alliance semic onductor 2575 augustine drive santa clara ca tel: 408-855-4900 fax: 408-855-4999 www.alsc.com rev 1.3 february 2005 asm3p2508a peak emi reducing solution features generates an emi optimized clocking signal at output. input frequency ? 14.31818 mhz. frequency outputs: o 120 mhz (modulated) - default. o 72 mhz (modulated) or 48 mhz (modulated) selectable via i2c 1% centre spread. modulation rate: 40 khz. byte write via i2c supply voltage range 3.3v 0.3v. available in 8-pin soic package. available in commercial and industrial temperature ranges. product description the asm3p2508a is a versatile spread spectrum frequency modulator. the asm3p2508a reduces electromagnetic interference (emi) at the clock source. the asm3p2508a allows significant system cost savings by reducing the number of circuit board layers and shielding that are required to pass emi regulations. the asm3p2508a modulates the output of pll in order to spread the bandwidth of a synthesized clock, thereby decreasing the peak amplitudes of its harmonics. this results in significantly lower system emi compared to the typical narrow band signal produced by oscillators and most clock generators. lowering emi by increasing a signal?s bandwidth is called spread spectrum clock generation. the asm3p2508a has a feature to power down the 72mhz/48mhz output by writing data into specific registers in the device via i2c. by writing a ?0? into bit 1 of byte 0, the pll block generating 72 mhz / 48mhz can be powered down. writing ?0? into bit ?7? of byte 1 selects an output of 72 mhz on fout2clk while a ?1? at the same location selects a 48 mhz clock output. however, the i2c block, crystal oscillator, and the pll block generating 120mhz would be always running. block diagram fout2clk (72 mhz / 48 mhz) sda crystal oscillator pll 1 scl xin xout v ss v dd fout1clk (120 mhz) i2c interface pll 2
peak emi reducing solution 2 of 11 rev 1.3 february 2005 asm3p2508a pin configuration pin description pin name type description xin i connection to crystal xout o connection to crystal v dd p power supply for the analog and digital blocks fout1clk o clock output-1 (120 mhz) - default fout2clk o clock output-2 ( 72 mhz / 48 mhz) sda i/o i2c data scl i i2c clock v ss p ground to entire chip fout1clk 8 7 6 5 fout2clk sda scl v s s xout 1 2 3 4 xin v dd asm3p2508a
peak emi reducing solution 3 of 11 rev 1.3 february 2005 asm3p2508a absolute maximum ratings symbol parameter rating unit v dd , v in voltage on any pin with respect to ground -0.5 to +7.0 v t stg storage temperature -65 to +125 c t a operating temperature 0 to 70 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std 22- a114-b) 2 kv n ote: these are stress ratings only and are not implied for functional use. exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. operating conditions parameter symbol condition / description min typ max unit supply voltage v dd 3.3v 10% 3 3.3 3.6 v ambient operating temperature range t a -10 +70 c crystal resonator frequency f xin 14.31818 mhz serial data transfer rate standard mode 10 100 kb/s output driver load capacitance c l 15 pf
peak emi reducing solution 4 of 11 rev 1.3 february 2005 asm3p2508a dc electrical characteristics (test condition : all the parameters are measured at room temperature (25c) , unless otherwise stated) parameter symbol conditions / description min typ max unit overall supply current, dynamic i cc v dd =3.3v, f clk =14.31818mhz, c l =15pf 40 49 60 ma supply current, static i dd v dd = 3.3v, software power down* 27 35 43 ma all input pins high-level input voltage v ih v dd =3.3v 2.0 - v dd +0.3 v low-level input voltage v il v dd =3.3v v ss -0.3 - 0.8 v high-level input current i ih -1 - 1 a low-level input current (pull-up) i il -20 -36 -80 a clock outputs (fout1clk, fout2clk ) high-level output voltage v oh v dd = 3.3v, i oh = 20ma 2.5 - 3.3 v low-level output voltage v ol v dd = 3.3v, i ol = 20ma 0 - 0.4 v z oh v o =0.5v dd ; output driving high - 29 - output impedance z ol vo=0.5v dd ; output driving low - 27 - * fout1clk (120mhz) is functional and not loaded
peak emi reducing solution 5 of 11 rev 1.3 february 2005 asm3p2508a ac electrical characteristics parameter symbol conditions/ description min typ max unit fout1clk 640 680 750 rise time t r v o = 0.8v to 2.0v; c l = 15pf fout2clk 440 480 600 ps fout1clk 660 720 800 fall time t f v o = 2.0v to 0.8v; c l = 15pf fout2clk 460 520 570 ps clock duty cycle t d ratio of pulse width (as measured from rising edge to next falling edge at 2.5v) to one clock period 45 - 55 % output frequency =120mhz - 2.73 - frequency deviation f d output frequency =72mhz /48 mhz - 1.78 - % on rising edges 500 us apart at 2.5 v relative to an ideal clock, pll b inactive * - 45 - jitter, long term tj (lt) on rising edges 500 us apart at 2.5 v relative to an ideal clock, pll b active * - 165 - ps from rising edge to next rising edge at 2.5 v, pll b inactive * - 110 - jitter, peak to peak tj ( o t) from rising edge to next rising edge at 2.5 v, pll b active * - 390 - ps clock stabilization time t stb output active from power up, run mode via software power down - 125 - p s * cl = 15 pf, fxin = 14.31818 mhz
peak emi reducing solution 6 of 11 rev 1.3 february 2005 asm3p2508a typical crystal oscillator circuit typical crystal specifications fundamental at cut parallel resonant crystal nominal frequency 14.31818 mhz frequency tolerance +/- 50 ppm or better at 25c operating temperature range -20c to +85c storage temperature -40c to +85c load capacitance 18pf shunt capacitance 7 pf maximum esr 25 q r1 = 510 q c1 = 27 pf c2 = 27 pf crystal
peak emi reducing solution 7 of 11 rev 1.3 february 2005 asm3p2508a i2c serial interface information the information in this section assumes familiarity with i2c programming. how to program asm3p2508a through i2c: master (host) sends a start bit. master (host) sends the write address d4 (h). asm3p2508a device will acknowledge. master (host) sends the beginning byte location (n = 0, 1). asm3p2508a device will acknowledge. master (host) sends a byte count (x = 1,2) asm3p2508a device will acknowledge. master (host) starts sending byte n through byte (n+x ? 1) asm3p2508a device will acknowledge each byte one at a time. master (host) sends a stop bit. controller (host) asm3p2508a (slave/receiver) start bit slave address d4(h) ack beginning byte location (=n) ack byte count (=x) ack beginning byte (byte n) ack next byte (byte n+1) ack ------- ---- last byte (byte n+x-1) ack stop bit how to read from asm3p2508a through i2c: master (host) will send start bit. master (host) sends the write address d4 (h). asm3p2508a device will acknowledge. master (host) sends the beginning byte location (n = 0, 1). asm3p2508a device will acknowledge. master (host) will send a separate start bit. master (host) sends the read address d5 (h). asm3p2508a device will acknowledge. asm3p2508a device will send the byte count (x = 1, 2). master (host) acknowledges. asm3p2508a device sends byte n through byte (n+x ? 1). master (host) will need to acknowledge each byte. master (host) will send a stop bit. controller (host) asm3p2508a (slave/receiver) start bit slave address d4(h) ack beginning byte = n ack repeat start slave address d5(h) ack byte count (= x) ack beginning byte n ack next byte n+1 ack ---- ------- last byte (byte n+x-1) not acknowledge stop bit
peak emi reducing solution 8 of 11 rev 1.3 february 2005 asm3p2508a an example of a byte write via i2c to partially ?power down? the device: asm3p2508a can be partially ?powered down? using bit 1 of byte 0. the organization of the register bits for byte ?0? is given with default values below: bit 7 6 5 4 3 2 1 0 resv resv resv resv resv resv pll2 enable pll1 enable 0 1 0 1 0 1 1 1 the function of partial power down of the device is of interest to us - that is bit 1 of byte 0. in the default mode this bit is logic ?1?. as such, the byte 0 default value is 57 (h). to put asm3p2508a in ?power down? mode, the bit 1 of byte 0 is to be changed to logic ?0?. hence writing a 55 (h) via i2c into byte 0 would put the device in partial ?power down? mode where the pll block generating 72 mhz / 48 mhz would be powered down while i2c block, crystal oscillator, and the pll block generating 120 mhz would still be active. the organization of the register bits is as below: bit 7 6 5 4 3 2 1 0 resv resv resv resv resv resv pll2 enable pll1 enable 0 1 0 1 0 1 0 1 byte 0 byte 1 fout1clk (mhz) fout2clk(mhz) power up default 6f(h) 3f(h) 120 72 48_mhz mode 6f(h) bf(h) 120 48 power down pll with 72mhz 6d(h) 3f(h) 120 - power down pll with 48mhz 6d(h) bf(h) 120 - figure showing a complete data transfer: .
peak emi reducing solution 9 of 11 rev 1.3 february 2005 asm3p2508a package information 8-pin soic package d e h d a 1 a2 a l c b e dimensions inches millimeters symbol min max min max a1 0.004 0.010 0.10 0.25 a 0.053 0.069 1.35 1.75 a2 0.049 0.059 1.25 1.50 b 0.012 0.020 0.31 0.51 c 0.007 0.010 0.18 0.25 d 0.193 bsc 4.90 bsc e 0.154 bsc 3.91 bsc e 0.050 bsc 1.27 bsc h 0.236 bsc 6.00 bsc l 0.016 0.050 0.41 1.27 s 0 8 0 8
peak emi reducing solution 10 of 11 rev 1.3 february 2005 asm3p2508a ordering codes part number marking package configuration temperature asm3p2508a-08-st 3p2508a 8-pin soic, tube commercial ASM3P2508A-08-SR 3p2508a 8-pin soic, tape and reel commercial asm3i2508a-08-st 3i2508a 8-pin soic, tube industrial asm3i2508a-08-sr 3i2508a 8-pin soic, tape and reel industrial asm3p2508af-08-st 3p2508af 8-pin soic, tube, pb free commercial asm3p2508af-08-sr 3p2508af 8-pin soic, tape and reel, pb free commercial asm3i2508af-08-st 3i2508af 8-pin soic, tube, pb free industrial asm3i2508af-08-sr 3i2508af 8-pin soic, tape and reel, pb free industrial device ordering information asm3p2508af-08sr licensed under us patent #5,488,627, #6,646,463 and #5,631,920. or - tsot23 -6,t/r sr - soic, t/r tt ? tssop, tube qr ? qfn, t/r tr - tssop, t/r qt - qfn, tray vt ? tvsop, tube bt - bga, tray vr ? tvsop, t/r br ? bga, t/r st ? soic, tube ur - sot-23,t/r pin count x = automotive i = industrial p or n/c = commercial (-40c to +125c) (-40c to +85c) (0c to +70c) 1 ? reserved 6 ? power management 2 - non pll based 7 ? power management 3 ? emi reduction 8 ? power management 4 ? ddr support products 9 ? hi performance 5 ? std zero delay buffer 0 - reserved alliance semiconductor mixed signal product part number lead free part
peak emi reducing solution 11 of 11 rev 1.3 february 2005 asm3p2508a ? copyright 2003 alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel# 408-855-4900 fax: 408-855-4999 www.alsc.com copyright ? alliance semiconductor all rights reserved preliminary information part number: asm3p2508a document version: v1.3 note: this product utilizes us patent # 6,646,463 impedance emulator patent issued to alliance semiconductor, dated 11-11-2003

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